Intelligent Memory Systems: Second InternationalWorkshop, IMS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers
Author: Frederic T. Chong, Christoforos Kozyrakis, Mark Oskin
Published by Springer Berlin Heidelberg
ISBN: 978-3-540-42328-7
DOI: 10.1007/3-540-44570-6
Table of Contents:
- A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
- Software Controlled Reconfigurable On-chip Memory for High Performance Computing
- Content-Based Prefetching: Initial Results
- Memory System Support for Dynamic Cache Line Assembly
- Adaptively Mapping Code in an Intelligent Memory Architecture
- The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆
- Memory Management in a PIM-Based Architecture
- Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
- FlexCache: A Framework for Flexible Compiler Generated Data Caching
- Aggressive Memory-Aware Compilation
- Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆
- SAGE: A New Analysis and Optimization System for FlexRAM Architecture
- Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
- The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
- Compiler-Directed Cache Line Size Adaptivity ⋆
- Summary of Question/Answer Sessions for Workshop Presentations
Includes bibliographical references and index
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